Various methods have been devised for organizing control over a bus when that bus is connected to more than one bus master. The problem is particularly significant where the bus masters are asynchronous since no common clock signal upon which to time connection events is present in such a system. One type of control frequently used for asynchronous bus masters is to serially connect the bus masters in a loop where the first bus master is the priority device and each succeeding device in the so-called "daisy-chain" is of lower priority. In systems of this kind, when a bus master desires access to the bus, it issues a Bus Request which is sent to a bus arbitrator to determine whether the bus is currently available. If the bus is available, a Bus Acknowledge signal is sent from the bus arbitrator to the first bus master, that is, the highest priority unit connected to the bus. Upon receipt of the Bus Acknowledge signal, the first bus master synchronizes that signal to its own local clock and determines whether it needs to access the bus. If it has a Local Bus Request outstanding, it seizes control of the bus and performs its operation. If the first bus master has no Bus Request outstanding, it passes the Bus Acknowledge signal to the second bus master. That bus master synchronizes the Bus Acknowledge signal with its local clock and then determines whether it has a Local Bus Request outstanding. If it does not, it passes the Bus Acknowledge signal along to the third bus master and so on until finally the bus master with a Bus Request outstanding receives it.
In the above-described system, significant time delay occurs at each bus master in synchronizing the received Bus Acknowledge signal to a local clock. However, synchronization must be performed before passing the signal along since if the first bus master fielded the Bus Acknowledge signal and seized control of the bus for itself and at the same time allowed the Bus Acknowledge signal to be passed along to subsequent bus masters, they would also initiate a process for seizing the bus. To correct that situation, the first bus master would then have to issue a Not Bus Acknowledge signal in order that the subsequent bus masters could then halt their processes already begun. The result would be confusion in the downstream bus masters from which recovery might be impossible. To prevent that, a synchronization circuit is established at each bus master to synchronize the receipt of the Bus Acknowledge signal to a local clock. That resulting delay can be significant in that the time used to synchronize the signal can be ten percent or more of the cycling time of the bus master. The object of this invention is to eliminate at least a portion of that delay.